The Early/normal signals refer to the synchronisation of the integration clocks. More or less quoted from the Journal of Electrical and Electronics Engineering, Australia, vol. 12, no. 2, June, 1992), the purpose of the Integration Clock is to produce a signal which defines the start of each integration to an accuracy of a fraction of a sample period. This enables the array control computer (xbones) to specify precisely the first sample of each integration. The major difficulty with this process arises from the fact that the phase of the sampler clock is continually being rotated. It follows that, with any fixed integration period, inevitably the situation will occur where the start time is close to a 128MHz sample time. Then the finite delays in the synchronization latching circuit will give rise to an uncertainty in the choice of the first sample of the integration. The circuit may choose the correct sample, as specified by the array control computer, or it may choose a neighbouring sample, approximately 8ns earlier or later. If the error is made, then this timing error will show up directly in any correlation function involving this input.
As the array control computer can calculate the time difference between the nominal start time and the first sample time in each integration, it can also predict when an error of the type described above is likely to occur. When this is the case, the array control computer sends a request to the integration clock to produce a start signal which is 4ns earlier than the nominal start time, hence avoiding the region of uncertainty. The chances of error are further reduced by using this early signal whenever the first sample time is within 2ns of the nominal start time and the normal start signal at other times.
In practise, the normal start signal will not coincide with the nominal start time, but will be offset by some initially unknown value. If the array control computer is to choose correctly between the early and the normal start signals, any such offset must first be calibrated. This is done by observing the sampler phase at which the 8ns delay error occurs in a correlation function involving the input being calibrated.